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1 ? isl8120irzec dual/n-phase buck pwm controller with integrated drivers the isl8120irzec integrates two voltage-mode synchronous buck pwm controllers to control a dual independent voltage regulator or a 2-phase single output regulator. it has pll circuits and can output a phase-shift- programmable clock signal for the system to be expanded to 3-, 4-, 6-, 12- phases with desired interleaving phase shift. it also integrates current sharing control for the power module to operate in parallel, which offers high system flexibility. it has voltage feed forward compensation to maintain a constant loop gain for optimal transient response, especially for applications with a wide input voltage range. its integrated high speed mosfet drivers and multi-feature functions provide complete control and protection for a 2/n-phase synchronous buck converter, dual independent regulators, or ddr tracking applications (vddq and vtt outputs). the output voltage of a isl8120irzec-based converter can be precisely regulated to as low as the internal reference voltage 0.6v, with a system accuracy of 0.9% over industrial temperature and line load variations. channel 2 can track an external ramp signal for ddr/tracking applications. the isl8120irzec integrates an internal linear regulator, which generates vcc from input rail for applications with only one single supply rail. the internal oscillator is adjustable from 150khz to 1.5mhz, and is able to track an external clock signal for frequency synchronization and phase paralleling applications. the integrated pre-biased digital soft-start, differential remote sensing amplifier, and programmable input voltage por features enhance the value of isl8120irzec. the isl8120irzec protects aga inst overcurrent conditions by inhibiting the pwm operation while monitoring the current with r ds(on) of the lower mosfet, dcr of the output inductor, or a precision resistor. it also has a pre-por overvoltage protection optio n, which provides some protection to the load device if the upper mosfet(s) is shorted. see ? pre-por overvoltage protection (pre-por- ovp) ? on page 24 for details. the isl8120irzec?s fault hand shake feature protects any channel from overloading/stressi ng due to system faults or phase failure. the undervoltage fault protection features are also designed to prevent a nega tive transient on the output voltage during falling down. this eliminates the schottky diode that is used in some systems for protecting the load device from reversed output voltage damage. features ? full traceability through assembly and test by date/trace code assignment ? enhanced process change notification per mil-prf-38535 ? enhanced obsolescence management ? wide vin range operation: 3v to 22v - vcc operation from 3v to 5.60v ? fast transient response - 80mhz bandwidth error amplifier - voltage-mode pwm leading-edge modulation control - voltage feed-forward ? dual channel 5v high speed 4a mosfet gate drivers - internal bootstrap diodes ? internal linear regulator prov ides a 5.4v bias from vin ? external soft-start ramp reference input for ddr/tracking applications ? excellent output voltage regulation - 0.6v 0.6%/0.9% internal reference over industrial temperature - true differential remote voltage sensing ? oscillator programmable from 150khz to 1.5mhz ? frequency synchronization ? scale for 1-, 2-, 3-, 4-, 6-, up to 12- phase with single output - excellent phase current balancing - programmable phase shift between the 2 phases controlled by the isl8120irzec and programmable phase shift for clockout signal - interleaving operation results in minimum input rms current and minimum output ripple current ? fault hand shake capability for high system reliability ? overcurrent protection - dcr, r ds(on) , or precision resistor current sensing - independent and average phase current ocp ? output overvoltage and undervoltage protections ? programmable phase shift in dual mode operation ? digital soft-start with pre-charged output start-up capability ? power-good indication ? dual independent channel enable inputs with precision voltage monitor and voltage feed-forward capability - programmable input voltage por and its hysteresis with a resistor divider at en input ? over-temperat ure protection ? pre-power-on-reset overvoltage protection option ? 32 ld 5x5 qfn package - near chip-scale footprint - enhanced thermal performance for mhz applications ? pb-free (rohs compliant) fn6763.1 data sheet april 21, 2009 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2008, 2009. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn6763.1 april 21, 2009 isl8120irzec applications ? power supply for datacom/telecom and pol ? paralleling power module ? wide and narrow input voltage range buck regulators ? ddr i and ii applications ? high current density power supplies ? multiple outputs vrm and vrd related literature ? technical brief tb389 ?pcb land pattern design and surface mount guidelines for qfn (mlfp) packages? pinout isl8120irzec (32 ld qfn) top view ordering information part number (note) part marking temp. range (c) package (pb-free) pkg. dwg. # isl8120irzec isl8120 irz -40 to +85 32 ld qfn l32.5x5b ISL8120IRZ-TEC* isl8120 irz -40 to +85 32 ld qfn l32.5x5b *please refer to tb347 for detai ls on reel specifications. note: these intersil pb-free plas tic packaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. fb1 vmon1 vsen1- vsen1+ isen1b isen1a vcc boot1 comp2 fb2 vmon2 vsen2- vsen2+ isen2b isen2a vin comp1 iset ishare en/vff1 fsync en/vff2 clkout/refin pgood ugate1 phase1 lgate1 pvcc lgate2 phase2 ugate2 boot2 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 910111213141516 33 gnd
3 fn6763.1 april 21, 2009 isl8120irzec block diagram (1/2) boot1 ugate1 phase1 fb1 comp1 lgate1 e/a1 pvcc vcc gate control internal reference en/ff1 pgood pgood comp1 vmon1 vin linear regulator ov/uv comp1 vsen1+ vsen1- soft-start and fault logic ocp v ref = 0.6v unity gain diff amp1 power-on reset (por) saw1 isen1a 1v pwm1 ics1 current correction + - pvcc i avg_cs channel 1 channel 1 current sampling 700mv vcc isen1b (bottom pad) gnd avg_ocp over-temperature protection (otp) i share 105 a 7-cycle delay 5.4v current correction i csh_err channel1 average ocp pgood v ref otp i csh_err figure 1. channel/phase 1 (vddq)
4 fn6763.1 april 21, 2009 isl8120irzec block diagram (2/2) boot2 ugate2 phase2 fb2 comp2 gnd lgate2 channel2 e/a2 pvcc isen2a gate control 105 a en/ff2 pgood pgood comp2 vmon2 ov/uv comp2 vsen2+ vsen2- fault logic ocp v ref unity gain diff amp2 por master clock fsync saw1 k*vddq + - pwm2 current correction ics2 ics2 ics1 + + i avg pvcc clkout/refin saw2 oscillator generator channel 2 soft-start and v ref2 channel 2 current sampling 700mv vcc relative phase control isen2b average current current share block ishare i csh_err + - - i avg_cs iset avg_ocp otp 7-cycle delay m/d control m/d = 1: multiphase i avg_cs = i avg or i cs1 i avg = (i cs1 + i cs2 ) / 2 i csh_err = (v isare - v iset )/g cs 0.6v =k*vddq v ref m/d = 0: dual output operation i avg_cs+15 a i avg_cs+15 a m/d control figure 2. channel/phase 2 (vtt)
5 fn6763.1 april 21, 2009 isl8120irzec typical application i (dual regulators with dcr sensing and remote sense) vout1 vout2 isl8120irzec q1 q2 comp1 fb1 vcc boot1 ugate1 isen1a lgate1 l in l out1 c hfin c boot1 c out1 r fb1 c f1 phase1 pvcc r fs fsync vin vsen1- r os1 pgood +3.3 to +22v vmon1 vsen1+ c sen1 v sense1- v sense1+ 10 10 c f3 z comp1 z fb1 q3 q4 comp2 fb2 boot2 ugate2 isen2a lgate2 l out2 c boot2 c out2 r isen2 r fb2 phase2 vsen2- r os2 vmon2 vsen2+ c sen2 v sense2- v sense2+ 10 10 z comp2 z fb2 vin_f vin_f clkout/refin ishare gnd isen1b c f2 isen2b r isen1 c bin r cc iset vcc r set 2k 2k en2/ff2 en1/ff1 vin
6 fn6763.1 april 21, 2009 isl8120irzec typical application ii (do uble data rate i or ii) 0.9v (ddr ii) 0.9v (ddr i) 1.25v v ddq v tt 1.8v (ddr ii) (ddr i) 2.5v isl8120irzec q1 q2 comp1 fb1 vcc boot1 ugate1 isen1a lgate1 l in l out1 c hfin c boot1 c out1 r fb1 c f1 phase1 pvcc r fs fsync vin vsen1- r os1 pgood +3.3 to +22v vmon1 vsen1+ c sen1 v sense1- v sense1+ 10 10 c f3 z comp1 z fb1 q3 q4 comp2 fb2 boot2 ugate2 isen2a lgate2 l out2 c boot2 c out2 r isen2 r fb2 phase2 vsen2- r os2 vmon2 vsen2+ c sen2 v sense2- v sense2+ 10 10 z comp1 z fb1 vin_f v ddq or vin_f clkout/refin gnd isen1b c f2 isen2b r isen1 c bin (v ddq /2) r cc ishare iset r set 2k 2k v ddq r vin r*(vddq/0.6-1) (see notes below) note 1: set the upper resistor to be a little higher than r*(vddq/0.6 - 1) will set the final refin voltage (stead state voltag e after soft-start) derived from the vddq to be a little higher than internal 0.6v reference. in this way, the vtt final voltage will use the internal 0.6v ref erence after soft-start. note 2: another way to set refin voltage is to connect vmon1 directly to refin pin. 1nf (or tie refin pin to vmon1 pin)
7 fn6763.1 april 21, 2009 isl8120irzec typical application iii (2 -phase operation with r ds(on) sensing and voltage trimming) l in c hfin c bin c f1 pvcc c f2 r cc +3v to +22v q1 q2 comp1/2 fb1 boot1 ugate1 lgate1 l out1 c boot1 c out1 r fb1 phase1 v out1 r fs fsync vin vsen1- r os1 pgood vmon1/2 vsen1+ c sen1 v sense1- v sense1+ 10 10 z comp1 q3 q4 boot2 ugate2 isen2a lgate2 c boot2 phase2 vsen2- vsen2+ vin_f vcc l out2 vcc en/ff1,2 clkout/refin gnd gnd isen2b fb2 isen1a r isen2 trim up pulled to v sense1- trim down pulled to v sense1+ isen1b r isen1 ishare iset r set c f3 dnp 0 vin isl8120irzec
8 fn6763.1 april 21, 2009 isl8120irzec typical application iv (3-phase regulat or with precision resistor sensing) c f1 pvcc c f2 r cc q1 q2 comp1/2 fb1 boot1 ugate1 lgate1 l out1 c boot1 phase1 en/ff1,2 vin vsen1- pgood vmon1/2 vsen1+ z comp1 q3 q4 boot2 ugate2 isen2a lgate2 c boot3 phase2 vsen2- vin_f vcc l out3 vcc en/ff1,2 vsen2+ gnd isen2b fb2 isen1a z fb1 l in c in c f1 pvcc c f2 r cc +3v to +22v q1 q2 comp1 fb1 boot1 ugate1 lgate1 l out2 c boot2 c out phase1 v out en/ff1 vin vsen1- pgood vmon1 vsen1+ v sense1- v sense1+ 10 10 c f3 boot2 ugate2 isen2a lgate2 phase2 vin_f vcc en/ff2 fsync ishare gnd vmon2 isen1a vin_f vin clkout/refin ishare r fs fsync clkout/refin c f3 vsen2- vsen2+ fb2 r fb1 r os1 c sen1 vcc gnd r isen3 isen1b vcc isen1b isen2b r isen2 r isen1 r isen1 gnd iset r r iset r r phase 1 and 3 isl8120irzec isl8120irzec phase 2
9 fn6763.1 april 21, 2009 isl8120irzec typical application v (4 pha se operation with dcr sensing) c f1 pvcc c f2 r cc q1 q2 comp1/2 fb1 boot1 ugate1 lgate1 l out1 c boot1 phase1 en/ff1,2 vin vsen1- pgood vmon1/2 vsen1+ z comp1 q3 q4 boot2 ugate2 isen2a lgate2 c boot3 phase2 vsen2- vin_f vcc l out3 vcc vsen2+ gnd isen2b fb2 isen1a z fb1 l in c in c f1 pvcc c f2 r cc +3v to +22v q1 q2 comp1/2 fb1 boot1 ugate1 lgate1 l out2 c boot2 c out phase1 v out1 vin r os1 pgood vmon1/2 v sense1- v sense1+ 10 10 c f3 q3 q4 boot2 ugate2 isen2a lgate2 c boot4 phase2 vsen1,2- vsen1,2+ vin_f vcc l out4 vcc en/ff1,2 fsync ishare gnd isen2b fb2 isen1a vin_f vin_f vin clkout/refin ishare r fs fsync clkout/refin c f3 phase 1 and 3 phase 2 and 4 r fb1 r os1 c sen1 2nd divider to avoid single point failure r fb1 vcc vcc isen1b r isen2 r isen4 isen1b r isen3 r isen1 vcc vcc c os iset r iset r r r isl8120irzec isl8120irzec
10 fn6763.1 april 21, 2009 typical application vi (3-phase regulator wi th resistor sensing and 1 phase regulator) c f1 pvcc c f2 r cc isl8120irzec q1 q2 comp1/2 fb1 boot1 ugate1 lgate1 l out1 c boot1 phase1 vin vsen1- pgood vmon1/2 vsen1+ z comp1 q3 q4 boot2 ugate2 isen2a lgate2 c boot3 phase2 vsen2- vsen2+ vin_f vcc l out3 vcc en/ff1, 2 vsen2+ gnd isen2b fb2 isen1a z fb1 l in c in c f1 pvcc c f2 r cc +3v to +22v isl8120irzec q1 q2 comp1 fb1 boot1 ugate1 lgate1 l out2 c boot2 c out1 phase1 v out1 en/ff1 vin vsen1- pgood vmon1 vsen1+ v sense1- v sense1+ 10 10 c f3 q3 q4 boot2 ugate2 isen2a lgate2 c boot4 phase2 vin_f vcc l out4 en/ff2 fsync ishare gnd vmon2 isen1a vin_f vin_f vin clkout/refin ishare r fs fsync clkout/refin c f3 v out2 v sense2- v sense2+ vsen2- vsen2+ 10 10 z fb2 z comp2 c out2 fb2 phase 1 and 3 phase 2 r fb1 r os1 c sen1 vcc gnd r isen3 isen1b r isen4 vcc vcc isen1b isen2b r isen2 r isen1 r isen1 iset r iset r r phase 2 r isl8120irzec
11 fn6763.1 april 21, 2009 isl8120irzec typical application vii (6 ph ase operation with dcr sensing) l in c in c f1 pvcc c f2 r cc +3v to +22v isl8120irzec q1 q2 comp1/2 fb1 boot1 ugate1 lgate1 l out3 c boot3 phase1 en/ff1, 2 vin vsen1- pgood vmon1/2 vsen1+ c f3 q3 q4 boot2 ugate2 isen2a lgate2 c boot6 phase2 vsen2- vsen2+ vin_f vcc l out6 vcc fsync ishare gnd isen2b fb2 isen1a vin_f clkout/refin c f1 pvcc c f2 r cc isl8120irzec q1 q2 comp1/2 fb1 boot1 ugate1 lgate1 l out1 c boot1 c out1 phase1 v out1 en/ff1, 2 vin vsen1- r os1 pgood vmon1 vsen1+ v sense1- v sense1+ 10 10 c f3 z comp1 q3 q4 boot2 ugate2 isen2a lgate2 c boot4 phase2 vsen2- vsen2+ vin_f vcc l out4 vcc fsync ishare gnd isen2b fb2 isen1a z fb1 c sen1 vin_f clkout/refin c f1 pvcc c f2 r cc isl8120irzec q1 q2 comp1/2 fb1 boot1 ugate1 lgate1 l out2 c boot2 phase1 en/ff1, 2 vin vsen1- pgood vmon1/2 vsen1+ c f3 q3 q4 boot2 ugate2 isen2a lgate2 c boot5 phase2 vsen2- vsen2+ vin_f vcc l out5 vcc fsync ishare gnd isen2b fb2 isen1a vin_f clkout/refin gnd gnd phase 2 and 5 phase 1 and 4 phase 3 and 6 vcc vcc vmon2 r fb1 r os1 r fb1 isen1b isen1b isen1b r isen1 r isen4 r isen2 r isen5 r isen3 r isen6 r iset r iset r iset r gnd vin r r
12 fn6763.1 april 21, 2009 isl8120irzec typical application viii (multip le power modules in parallel with current sharing control) c f1 pvcc c f2 r cc1 isl8120irzec q1 q2 comp1/2 fb1 boot1 ugate1 lgate1 l out1 c boot1 phase1 en/ff1, 2 vin vsen1- pgood vmon1/2 vsen1+ z comp1 q3 q4 boot2 ugate2 isen2a lgate2 c boot2 phase2 vin_f vcc l out2 gnd isen2b isen1a z fb1 l in c in c f4 pvcc c f5 r cc2 +3v to +22v isl8120irzec q5 q6 fb1 boot1 ugate1 lgate1 l out3 c boot3 c out2 phase1 v out2 vin pgood vmon1/2 v sense2 + 10 10 c f6 q7 q8 boot2 ugate2 isen2a lgate2 c boot4 phase2 vsen2- vsen2+ vin_f vcc l out4 en/ff1, 2 fsync ishare gnd isen2b fb2 isen1a vin_f vin_f vin clkout/refin ishare r fs fsync clkout/refin c f3 2-phase 2-phase r fb1 r os1 c sen1 isen1b r isen3 r isen4 isen1b r isen2 r isen1 gnd iset r iset r r r c out1 v out1 v sense1- v sense1+ 10 10 comp1/2 vsen1- vsen1+ z comp2 z fb2 r fb2 r os2 c sen2 v sense2- vsen2- vsen2+ vcc fb2 gnd r csr1 r csr2 vcc v load module #1 module #2
13 fn6763.1 april 21, 2009 typical application viiii (4 out puts operation wi th dcr sensing) c out3 v out3 v sense3- v sense3+ 2 2 l in c in c f1 pvcc c f2 r cc isl8120irzec q1 q2 comp1 fb1 boot1 ugate1 lgate1 l out3 c boot3 phase1 en/ff1 vin vsen1- pgood vmon1 vsen1+ c f3 q3 q4 boot2 ugate2 isen2a lgate2 c boot6 phase2 vsen2- vsen2+ vin_f vcc l out6 en/ff2 fsync ishare/iset gnd isen2b fb2 isen1a vin_f clkout/refin c f1 pvcc c f2 r cc isl8120irzec q1 q2 comp1/2 fb1 boot1 ugate1 lgate1 l out1 c boot1 c out1 phase1 v out1 en/ff1, 2 vin vsen1- r os1 pgood vmon1 vsen1+ v sense1- v sense1+ 2 2 c f3 z comp1 q3 q4 boot2 ugate2 isen2a lgate2 c boot4 phase2 vsen2- vsen2+ vin_f vcc l out4 vcc fsync ishare/iset gnd isen2b fb2 isen1a z fb1 c sen1 vin_f clkout/refin c f1 pvcc c f2 r cc isl8120irzec q1 q2 comp1/2 fb1 boot1 ugate1 lgate1 l out2 c boot1 phase1 en/ff1, 2 vin vsen1- pgood vmon1/2 vsen1+ c f3 q3 q4 boot2 ugate2 isen2a lgate2 c boot2 phase2 vsen2- vsen2+ vin_f vcc l out5 vcc fsync ishare/iset gnd isen2b fb2 isen1a vin_f clkout/refin gnd gnd output 2 output 1 output 3 and 4 vmon2 r fb1 r os1 r fb1 isen1b isen1b isen1b r isen1 r isen4 r isen2 r isen5 r isen3 r isen6 z comp2 z fb2 v out2 v sense2- v sense2+ 2 c out2 2 r os2 c sen2 r fb2 r os3 c sen3 r fb3 z fb3 c out4 v out4 v sense4- v sense4+ 2 2 r os4 c sen4 r fb4 comp2 z comp4 z fb3 vmon2 (phase 1 and 4) (phase 2 and 5) (phase 3 and 6) +3v to +22v vin r r r isl8120irzec
14 fn6763.1 april 21, 2009 absolute maximum rati ngs thermal information input voltage, vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +27v driver bias voltage, pvcc . . . . . . . . . . . . . . . . . . . . -0.3v to +6.5v signal bias voltage, vcc . . . . . . . . . . . . . . . . . . . . . -0.3v to +6.5v boot/ugate voltage, v boot . . . . . . . . . . . . . . . . . . -0.3v to +36v phase voltage, v phase . . . . . . . . . . v boot - 7v to v boot + 0.3v boot to phase voltage, v boot - v phase . . -0.3v to vcc +0.3v input, output or i/o voltage . . . . . . . . . . . . . . . . -0.3v to vcc +0.3v recommended operating conditions input voltage, vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3v to 22v driver bias voltage, pvcc . . . . . . . . . . . . . . . . . . . . . . . 3v to 5.6v signal bias voltage, vcc . . . . . . . . . . . . . . . . . . . . . . . . 3v to 5.6v boot to phase voltage (overcharged), v boot - v phase . . . . . .<6v industrial ambient temperature range . . . . . . . . . . .-40c to +85c maximum junction temperature range . . . . . . . . . . . . . . . . +125c thermal resistance (typical notes 1, 2) ja (c/w) jc (c/w) 32 ld qfn package . . . . . . . . . . . . . . 32 3.5 maximum junction temperature . . . . . . . . . . . . . . .-55c to +150c maximum storage temperature range . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 1. ja is measured in free air with the component mounted on a high effe ctive thermal conductivity test board with ?direct attach? fe atures. 2. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 3. limits should be considered typi cal and are not production tested. electrical specifications recommended operating conditions, unless otherwise not ed. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. tem perature limits established by characterization and are not production tested. parameter symbol test conditions min typ max units vcc supply current nominal supply vin current i q_vin vin = 20v; vcc = pvcc; no load; f sw = 500khz 11 15 20 ma nominal supply vin current i q_vin vin=3.3v;vcc = pvcc; no load; f sw = 500khz 81214ma shutdown supply pvcc current i pvcc en = 0v, pvcc = 5v 0.5 1 1.4 ma shutdown supply vcc current i vcc en = 0v, vcc = 3v 7 10 12 ma internal linear regulator maximum current (note 3) i pvcc pvcc = 4v to 5.6v 250 ma pvcc = 3v to 4v 150 ma saturated equivalent impedance (note 3) r ldo p-channel mosfet (vin = 5v) 1 pvcc voltage level pvcc i pvcc = 0ma to 250ma 5.1 5.4 5.6 v power-on reset rising vcc threshold 2.85 3 v falling vcc threshold 2.65 2.75 v rising pvcc threshold 2.85 3.05 v falling pvcc threshold 2.65 2.75 v system soft-start delay (note 3) t ss_dly after pll, vcc, and pvcc pors, and en(s) above their thresholds 384 cycles enable turn-on threshold voltage 0.75 0.8 0.86 v hysteresis sink current i en_hys 25 30 35 a undervoltage lockout hysteresis (note 3) v en_hys v en_rth = 10.6v; v en_fth = 9v r up = 53.6k , r down = 5.23k 1.5 v sink current i en_sink 15 ma sink impedance r en_sink i en_sink = 5ma 65 isl8120irzec
15 fn6763.1 april 21, 2009 oscillator oscillator frequency range 150 1500 khz oscillator frequency r fs = 100k, figure 20 344 377 406 khz total variation vcc = 5v; -40c < t a <+85c -9 +9 % peak-to-peak ramp amplitude v ramp vcc = 5v, v en = 0.8v 1 v p-p linear gain of ramp over v en g ramp g ramp = v ramp /v en 1.25 ramp peak voltage v ramp_peak v en = vcc vcc - 1.4 v peak-to-peak ramp amplitude v ramp v en = vcc = 5.4v, r up = 2k 3 v p-p peak-to-peak ramp amplitude v ramp v en = vcc = 3v; r up = 2k 0.6 v p-p ramp amplitude upon disable v ramp v en = 0v; vcc = 3.5v to 5.5v 1 v p-p ramp amplitude upon disable v ramp v en = 0v; vcc < 3.4v vcc - 2.4 v p-p ramp dc offset v ramp_os 1v frequency synchronization and phase lock loop synchronization frequency vcc = 5.4v (3v) 150 1500 khz pll locking time vcc = 5.4v (3v); f sw = 400khz; 105 s input signal duty cycle range (note 3) 10 90 % pwm minimum pwm off time t min_off 310 345 410 ns current sampling blanking time (note 3) t blanking 175 ns reference channel 1 reference voltage (include error and differential amplifiers? offsets) v ref1 0.6 v -0.7 0.7 % channel 2 reference voltage (include error and differential amplifiers? offsets) v ref2 0.6 v -0.75 0.95 % error amplifier dc gain (note 3) r l = 10k, c l = 100p, at comp pin 98 db unity gain-bandwidth (note 3) ugbw_ea r l = 10k, c l = 100p, at comp pin 80 mhz input common mode range (note 3) -0.2 vcc - 1.8 v output voltage swing vcc = 5v 0.85 vcc - 1.0 v slew rate (note 3) sr_ea r l = 10k, c l = 100p, at comp pin 20 v/s input current (note 3) i fb positive direction into the fb pin 100 na output sink current i comp 3ma output source current i comp 6ma disable threshold (note 3) v vsen- vcc - 0.4 v differential amplifier dc gain (note 3) ug_da unity gain amplifier 0 db unity gain bandwidth (note 3) ugbw_da 5 mhz negative input source current (note 3) i vsen- 100 na maximum source current for current sharing (typical application viii) (note 3) i vsen1- vsen1- source current for current sharing when parallel multiple modules each of which has its own voltage loop 350 a input impedance r vsen+_to _vsen- 1m output voltage swing (note 3) 0 vcc - 1.8 v input common mode range (note 3) -0.2 vcc - 1.8 v electrical specifications recommended operating conditions, unless otherwise not ed. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. tem perature limits established by characterization and are not production tested. (continued) parameter symbol test conditions min typ max units isl8120irzec
16 fn6763.1 april 21, 2009 disable threshold (note3) v vsen- v mon1,2 = tri-state vcc - 0.4 v gate drivers upper drive source resistance r ugate 45ma source current 1.0 upper drive sink resistance r ugate 45ma sink current 1.0 lower drive source resistance r lgate 45ma source current 1.0 lower drive sink resistance r lgate 45ma sink current 0.4 overcurrent protection channel overcurrent limit (note 3) i source vcc = 3v to 5.6v 108 a channel overcurrent limit i source vcc = 5v 89 108 122 a share pin oc threshold v oc_set vcc = 3v to 5.6v (comparator offset included) 1.16 1.20 1.22 v share pin oc hysteresis (note 3) v oc_set_hys vcc = 3v to 5.6v (comparator offset included) 50 mv current share internal balance accuracy (note 3) vcc = 3v and 3.6v, 1% resistor sense, 10mv signal 5 % internal balance accuracy (note 3) vcc = 4.5v and 5.6v, 1% resistor sense, 10mv signal 5 % external current share accuracy (note 3) vcc = 3v and 5.6v, 1% resistor sense, 10mv signal 5 % power good monitor undervoltage falling trip point v uvf percentage below reference point -15 -13 -11 % undervoltage rising hysteresis v uvr_hys percentage above uv trip point 4 % overvoltage rising trip point v ovr percentage above reference point 11 13 15 % overvoltage falling hysteresis v ovf_hys percentage below ov trip point 4 % pgood low output voltage i pgood = 2ma 0.35 v sinking impedance i pgood = 2ma 70 maximum sinking current (note 3) v pgood < 0.8v 10 ma overvoltage protection ov latching up trip point en/ff= ugate = latch low, lgate = high 118 120 122 % ov non-latching up trip point (note 3) en/ff = low, ugate = low, lgate = high 113 % lgate release trip point en/ff = low/high, ugate = low, lgate = low 87 % over-temperature protection over-temperature trip (note 3) 150 c over-temperature release threshold (note 3) 125 c electrical specifications recommended operating conditions, unless otherwise not ed. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. tem perature limits established by characterization and are not production tested. (continued) parameter symbol test conditions min typ max units isl8120irzec
17 fn6763.1 april 21, 2009 functional pin description gnd (pin 33, signal and power ground pad) all voltage levels are referenced to this pad.this pad provides a return path for the low-side mosfet drives and internal power circuitries as well as all analog signals. connect this pad to the circuit ground using the shortest possible path (more than 5 to 6 via to the internal ground plane, placed on the soldering pad are recommended). vin (pin 16, internal linear regulator input) this pin should be tied directly to the input rail when using the internal linear regulator. it provides power to the internal linear drive circuitry. when used with an external 5v supply, this pin should be tied directly to pvcc. the internal linear device is protected against reverse bias generated by the remaining charge of the decoupling capacitor at pvcc when losing the input rail. vcc (pin 26, analog circuit bias) this pin provides power for the analog circuitry. a rc filter is recommended between the connection of this pin to a 3v to 5.6v bias (typically pvcc). r is suggested to be a 5 resistor. and in 3.3v applicatio ns, the r could be shorted to allow the low end input in concerns of the vcc falling threshold. the vcc decoupl ing cap c is strongly recommended to be as large as 10f ceramic capacitor. this pin can be powered either by the internal linear regulator or by an external voltage source. boot1, 2 (pins 25, 17) this pin provides the bootstrap bias for the high-side driver. internal bootstrap diodes connected to the pvcc pin provide the necessary bootstrap charge. its typical operational voltage range is 2.5v to 5.6v. ugate1, 2 (pin 24, 8) these pins provide the drive for the high-side devices and should be connected to the mosfets? gates. phase1, 2 (pins 23,19) connect these pins to the source of the high-side mosfets and the drain of the low-side mosfets. these pins represent the return path for the high-side gate drives. pvcc (pin 21, driver bias voltage) this pin is the output of the internal series linear regulator. it provides the bias for both low-side and high-side drives. its operational voltage range is 3v to 5.6v. the decoupling ceramic capacitor in the pvcc pin is 10f. lgate1, 2 (pins 22, 20) these pins provide the drive for the low-side devices and should be connected to the mosfets? gates. fsync (pin 5) the oscillator switching frequen cy is adjusted by placing a resistor (r fs ) from this pin to gnd. the internal oscillator will lock to an external frequency source if this pin is connected to a switching square pulse waveform, typically the clkout input signal from another isl8120irzec or an external clock. the internal oscillator synchronizes with the leading edge of the input signal. en/ff1, 2 (pins 4, 6) t hese are triple function pins. the input voltages to these pins are compared with a prec ision 0.8v reference and enable their digital soft-starts. by pulling this pin to voltage lower than the threshold, the corresponding channel can be disabled independently. connecting these pins to input bus through a voltage resistor divider can monitor the input voltage. the undervoltage lockout and its hysteresis levels can be programmed by setting the values of the resistor dividers. the voltages on these pins are also fed into controller to be used to adjust the amplitude of each individual sawtooth independently. furthermore, during fault (such as overvoltage, overcurrent, and over-temperature) conditions, these pins (en/ff_) are used to communicate the information to other cascaded ics by pulling low. pgood (pin 8) provides an open drain power-good signal when both channels are within 9% of nominal output regulation point with 4% hysteresis (13%/9%) and soft-start is complete. pgood monitors the outputs (vmon1/2) of the internal differential amplifiers. isen1a, 2a (pins 27, 15) these pins are the positive inputs of the current sensing amplifier. together with isen1b,2b, these pins provide r ds(on) , dcr, or precision resistor current sensing. isen1b, 2b (pins 28, 14) these pins are the negative inputs of the current sensing amplifier. together with the isen1a, 2a pins they provide r ds(on) , dcr, or precision resistor current sensing. refer to ? typical application iii (2-phase operation with r ds(on) sensing and voltage trimming) ? on page 7 for r ds(on) sensing set up and ? typical application v (4 phase operation with dcr sensing) ? on page 9 for dcr sensing set-up. iset (pin 2) this pin sources an 15a offset current plus the average current of both channels in multiphase mode or only channel 1?s current in independent mode. the voltage (v iset ) set by an external resistor (r iset ) represents the average current level of the local active channel(s). v iset is compared with a 1v threshold for average overcurrent protections. for full-scale current, r iset should be 1v/120a = 8.33k . typically 10k is used for r set . isl8120irzec
18 fn6763.1 april 21, 2009 ishare (pin 3) this pin is used for current sharing purposes and is configured to current share bus representing all modules? average current. it sources 15 a offset current plus the average current of both channels in multiphase mode or channel 1?s current in independent mode. the share bus (ishare pins connected together) voltage (v ishare ) set by an external resistor (r ishare ) represents the average current level of all active channel(s). the ishare bus voltage compares with each reference voltage set by each r iset and generates current share error signal for current correction block of each cascaded controller. the share bus impedance r ishare should be set as r iset /n ctrl (r iset divided by number of active current sharing controllers). clkout/refin (pin 7) this pin has a dual function depending on the mode in which the chip is operating. it provides clock signal to synchronize with other isl8120(s) with its vsen2- pulled within 700mv of vcc for multiphase (3-, 4-, 6-, 8-, 10-, or 12-phase) operation. when the vsen2- pi n is not within 700mv of vcc, isl8120 is in dual mode (dual independent pwm output). the clockout signal of this pin is not available in this mode, but the isl8120 can be synchronized to external clock. in dual mode, this pin works as the following two functions: 1. an external reference (0.6v target only) can be in place of the channel 2?s internal reference through this pin for ddr/tracking applications (see ? internal reference and system accuracy ? on page 31). 2. the isl8120irzec operates as a dual-pwm controller for two independent regulators with selectable phase degree shift, which is programmed by the voltage level on refin (see ? ddr and dual mode operation ? on page 30). fb1, 2 (pins 32, 10) these pins are the inverting inputs of the error amplifiers. these pins should be connected to vmon1, 2 with the compensation feedback network. no direct connection between fb and vmon pins is allowed. with vsen2- pulled within 700mv of vcc, the corresponding error amplifier is disabled and the amplifier?s output is high impedance. fb2 is one of the two pins to determine the relative phase relationship between the internal clock of both channels and the clkout signal. see ? ddr and dual mode operation ? on page 30. comp1, 2 (pins 1, 9) these pins are the error amplifier outputs. they should be connected to fb1, 2 pins through desired compensation networks when both channels are operating independently. when vsen1-, 2- are pulled within 700mv of vcc, the corresponding error amplifier is disabled and its output (comp pin) is high impedance. thus, in multiphase operations, all other slave phases? comp pins can tie to the master phase?s comp1 pin (1 st phase), which modulates each phase?s pwm pulse with a single voltage feedback loop. while the error amplifier is not disabled, an independent compensation network is required for each cascaded ic. vsen1+, 2+ (pins 29, 13) these pins are the positive inputs of the standard unity gain operational amplifier for differential remote sense for the corresponding channel (channel 1 and 2), and should be connected to the positive rail of the load/processor. these pins can also provide precision output voltage trimming capability by pulling a resistor from this pin to the positive rail of the load (trimming down) or the return (typical vsen1-2-pins) of the load (tri mming up). the typical input impedance of vsen+ with respect to vsen- is 500k . by setting the resistor divider conn ected from the output voltage to the input of the differential amplifier, the desired output voltage can be programmed. to minimize the system accuracy error introduced by the input impedance of the differential amplifier, a 100 or less resistor is recommended to be used for the lower leg (r os ) of the feedback resistor divider. with vsen2- pulled within 700mv of vcc, the corresponding error amplifier is disabled and vsen2+ is one of the two pins to determine the relative phase relationship between the internal clock of both channels and the clkout signal. see ? ddr and dual mode operation ? on page 30 for details. vsen1-, 2- (pins 30, 12) these pins are the negative inputs of standard unity gain operational amplifier for differential remote sense for the corresponding regulator (channel 1 and 2), and should be connected to the negative ra il of the load/processor. when vsen1-, 2- are pulled within 700mv of vcc, the corresponding error amplifier and differential amplifier are disabled and their outputs are high impedance. both vsen2+ and fb2 input signal levels determine the relative phases between the internal controllers as well as the clkout signal. see ? ddr and dual mode operation ? on page 30 for details. when configured as multiple power modules (with independent voltage loop) operating in parallel, in order to implement the current sharing c ontrol, a resistor needs to be inserted between vsen1- pin and output vo ltage negative sense point (between vsen1- and lower voltage sense resistor), as shown in the ? typical application viii (multiple power modules in parallel with current sharing control) ? on page 12. this introduces a correction voltage for the modules with lower load current to keep the current distribution balanced among modules. the module with the highest load current will autom atically become the master module. the recommended value for the vsen1- resistor is isl8120irzec
19 fn6763.1 april 21, 2009 100 and it should not be large in order to keep the unit gain amplifier input impedance compatibility. vmon1, 2 (pins 31, 11) these pins are outputs of the uni ty gain amplifiers. they are connected internally to the ov/uv/pgood comparators. these pins should be connected to the fb1, 2 pins by a standard feedback network when both channels operating independently. when vsen1-, 2- are pulled within 700mv of vcc, the corresponding differential amplifier is disabled and its output (vmon pin) is high impedance. in such an event, the vmon pin can be used as an additional monitor of the output voltage with a resistor divider to protect the system against single point of failur e, which occurs in the system using the same resistor divider for both of the uv/ov comparator and output voltage feedback. modes of operation there are 9 typical operation modes depending upon the signal levels on en1/ff1, en2/ff2, vsen2+, vsen2-, fb2, and clkout/refin. mode 1: the ic is completely disabled when en1/ff1 and en2/ff2 are pulled below 0.8v. mode 2: with en1/ff1 pulled low and en2/ff2 pulled high (mode 2a), or en1/ff1 pulled high and en2/ff2 pulled low (mode 2b), the isl8120irzec operates as a single phase regulator. the current sourcing out from the ishare pin represents the first channel current plus 15a offset current. mode 3: when vsen2- is used as a negative sense line, both channels? phase shift depends upon the voltage level of clkout/refin. when the clkout/refin pin is within 29% to 45% of vcc, channel 2 delays 0 over channel 1 (mode 3a); when within 45% to 62% of vcc, 90delay (mode 3b); when greater than 62% to vcc, 180 delay (mode 3c). refer to the ? ddr and dual mode operation ? on page 30. mode 4: when vsen2- is used as a negative remote sense line, and clkout/refin is connected to a external voltage ramp lower than the internal soft-start ramp and lower than 0.6v, the external ramp signal will replaces channel 2?s internal soft-start ramp to be tracked at start-up, controller operating in ddr mode. the controller will use the lowest voltage among the internal 0.6v reference, the external voltage in clkout/refin pin and the soft-start ramp signal. channel 1 is delayed 60 behind channel 2. refer to the ? ddr and dual mode operation ? on page 30. mode 5: with vsen2- pulled within 700mv of vcc and fb2 pulled to ground, the internal channels are 180 out-of-phase and operate in 2-phase single output mode (5a). the clkout/refin pin (rising edge) also signals out clock with 60 phase shift relative to the channel 1?s clock signal (falling edge of pwm) for 6-phase operation with two other isl8120irzecs (5b). when the share pins are not connected to each other for the three ics in sync, two of which can operate in mode 5a (3 independent outputs can be generated (mode 5d)) and m odes 3 and 4 (to generate 4 independent outputs (mode 5c)) respectively. mode 6: with vsen2- pulled within 700mv of vcc, fb2 pulled high and vsen2+ pulled low, the internal channels (as 1 st and 3 rd phase, respectively) are 240 out-of-phase and operate in 3-phase single output mode, combined with another isl8120irzec at mode 2b. the clkout/refin pin signals out 120 relative phases to the falling edge of channel 1?s clock signal to synchronize with the second isl8120irzec?s channel 1 (as 2 nd phase). mode 7: with vsen2- pulled within 700mv of vcc and fb2 and vsen2+ pulled high, the internal channels is 180 out-of-phase. the clkout/refin pin (rising edge) signals out 90 relative phase to the channel 1?s clock signal (falling edge of pwm) to synchronize with another isl8120irzec, which can operate at mode 3, 4, 5a, or 7a. a 4-phase single output converter can be constructed with two isl8120irzecs operating in mode 5a or 7a (mode 7a). if the share bus is not connected between ics, each ic could generate an independent output (mode 7b). when the second isl8120irzec operat es as two independent regulators (mode 3) or in ddr mode (mode 4), then three independent output system is generated (mode 7c). both ics can also be constructed as a 3-phase converter (0, 90, and 180, not a equal phase shift for 3-phase) with a single phase regulator (270). mode 8 : the output clkout signal allows expansion for 12-phase operation with the ca scaded sequencing as shown in table 1. no external clock is required in this mode for the desired phase shift. mode 9: with an external clock, the part can be expanded for 5, 7, 8, 9 10 and 11 phase single output operation with the desired phase shift. isl8120irzec
20 fn6763.1 april 21, 2009 table 1. 1st ic (i = input; o = output; i/o = input and output, bi-direction) modes of operation output (see description for details) operation mode of 2 nd ic operation mode of 3 rd ic mode en1/ ff1 (i) en2/ ff2 (i) vsen2- (i) fb2 (i) vsen2 + (i) clkout/refin wrt 1st (i or o) ishare (i/o) represents which channel(s) current 2nd channel wrt 1st (o) (note) 100 - - - - - - - - disabled 2a 0 1 active active active - n/a vmon1 = vmon2 to keep pgood valid --single phase 2b 1 0 - - - - 1 st channel vmon1 = vmon2 to keep pgood valid --single phase 3a - - 62% of vcc (i) 1 st channel 180 - - dual regulator 4 - - 12) note: ? 2nd channel wrt 1st ? is referred to as ?channel 2 lag channel 1 by the degrees specified by the number in the corresponding table cells?. for example, 90 with 2nd channel wrt 1st means channel 2 lags channel 1 by 90; -60 with 2nd channel wrt 1st means channel 2 leads channel 1 by 60. isl8120irzec
21 fn6763.1 april 21, 2009 vsen2- vsen2+ vmon2 uv/ov 700mv vcc figure 3. simplified relative phases control diff error amp2 comp2 amp2 comp2 channel 1 pwm control block channel 2 pwm control block v ref2 = v ref fb2 clock generator and relative phases control clkout/refin ch1 ug (1 st ic) d 1-d clkout (1 st ic) ch2 ug (1 st ic) ch2 ug (2 nd ic) 50% d d 180 d ch1 ug (2 nd ic) 90 180 ch1 ug (1 st ic) d 1-d clkout (1 st ic) ch2 ug (1 st ic) ch2 ug(2 nd ic, off, en2/ff2 = 0) 50% d 240 ch1 ug (2 nd ic) 120 3- p hase timing diagram (mode 6 ) d 1-d 120 90 4-phase timing diagram (mode 7a) isl8120irzec
22 fn6763.1 april 21, 2009 functional description initialization initially, the isl8120irzec power-on reset (por) circuits continually monitor the bias voltages (pvcc and vcc) and the voltage at en pin. the por function initiates soft-start operation 384 clock cycles after the en pin voltage is pulled to be above 0.8v, all input supplies exceed their por thresholds and the pll locking time expires, as shown in figure 4. the enable pin can be used as a voltage monitor and to set desired hysteresis with an internal 30 a sinking current going through an external resistor divider. the sinking current is disengaged after the system is enabled. this feature is especially designed for applications that require higher input rail por for better undervoltage protection. for example, in 12v applications, r up = 53.6k and r down = 5.23k will set the turn-on threshold (v en_rth ) to 10.6v and turn-off threshold (v en_fth ) to 9v, with 1.6v hysteresis (v en_hys ). during shutdown or fault conditions, the soft-start is reset quickly while ugate and lgate changes states immediately (<100ns) upon the input drops below falling por. . voltage feed-forward other than used as a voltage monitor described in previous section, the voltages applied to the en/ff pins are also fed to adjust the amplitude of each channel?s individual sawtooth. the amplitude of each channel?s sawtooth is set to 1.25 times of the corresponding en/ff voltage upon its enable (above 0.8v). this helps to maintain a constant gain ( ) contri buted by the modulator and the input voltage to achieve optimum loop response over a wide input voltage range. the sawtooth ramp offset voltage is 1v (equal to 0.8v*1.25), and the peak of the sawtooth is limited to vcc - 1.4v. with vcc = 5.4v, the ramp has a maximum peak-to-peak amplitude of vcc - 2.4v (equal to 3v); so the feed-forward voltage effective range is typically 3x as the ramp amplitude ranges from 1v to 3v. a 384 cycle delay is added after the system reaches its rising por and prior to the soft-start. the rc timing at the en/ff pin should be sufficiently small to ensure that the input bus reaches its static state and the internal ramp circuitry stabilizes before soft-start. a large rc could cause the internal ramp amplitude not to synchronize with the input bus voltage during output start- up or when recovering from faults. it is recommended to us e open drain or open collector to gate this pin for any system delay, as shown in figure 5. the multiphase system can immediately turn off all ics under fault conditions of one or more phases by pulling all en/ff pins low. thus, no bouncing occurs among channels at fault and no single phase could carry all current and be over stressed. figure 4. soft-start initialization logic vcc por pvcc por en1/ff1 por soft-start high = above por; low = below por of channel 1 and 384 vcc por pvcc por en2/ff2 por soft-start of channel 2 and pll locking cycles 384 cycles figure 5. simplified enable and voltage feedforward circuit 0.8v i en_hys = 30 a r up r down soft-start r down r up v ? en_ref v en_fth v en_ref ? -------------------------------------------------------------- - = v en_fth v en_rth v en_hys ? = vin g ramp = 1.25 limiter sawtooth amplitude v ramp limit(v cc_ff g ramp , vcc - 1.4v - v ramp_offset ) = ( v ramp ) en/ff ov, ot, oc, and pll locking faults (only for en/ff1) r up v en_hys i en_hys ---------------------------- - = system delay v cc_ff vcc 0.8v v ramp_offset = 1.0v vcc - 1.4v lower limit upper limit (ramp offset) 384 clock cycles g m vin d max v ramp ? ? = isl8120irzec
23 fn6763.1 april 21, 2009 while en/ff is pulled to ground, a constant voltage (0.8v) is fed into the ramp generator to maintain a minimum peak-to-peak ramp . since the en/ff pins are pulled down under fault conditions, the pull-up resistor (r up ) should be scaled to sink no more than 5ma current from en/ff pin. essentially, the en/ff pins cannot be directly connected to vcc. soft-start the isl8120irzec has two independent digital pre-charged soft-start circuitry, which has a rise time inversely proportional to the switching frequency and is determined by an digital counter that increments with every pulse of the phase clock. refer to figure 7. the full soft-start time from 0v to 0.6v can be estimated by equation 1. the isl8120irzec has the ability to work under a pre-charged output (see figure 8). the output voltage would not be yanked down during pre- charged start-up. if the pre- charged output voltage is greater than the final target level but prior to 113% setpoint, the switching will not start until the output voltage reduces to the target voltage and the first pwm pulse is generated (see figure 9). the maximum allowable pre-charged level is 113%. if the pre-charged level is above 113% but below 120%, the output will hiccup between 113% (lgate turns on) and 87% (lgate turns off) while en/ff is pulled low. if the pre-charged load voltage is above 120% of the targeted ou tput voltage, then the controller will be latched off and not be able to power-up. see ? pre-por overvoltage pr otection (pre-por-ovp) ? on page 24 for details. for above target pre-charged start-up, the output voltage would not change until the end of the soft-start. if the initial dip is below the uv level, the lgate could be turned off. in such an event, the body-diode drop of the low-side fet will be sensed and could potentiality cause an ocp event for r ds(on) current sensing applications. power-good figure 6. typical 4-phase with fault handshake en/ff1 en/ff2 2-phase en/ff1 en/ff2 2-phase isl8120irzec isl8120irzec r up r down vin r up v en_hys i en_hys n phase ? --------------------------------------------------------- - = t ss 1280 f sw ------------ - = (eq. 1) vout 0.0v t ss 1280 f sw ------------ - = first pwm pulse -100mv t ss_dly 384 f sw ------------ figure 7. soft-start with vout = 0v ss settling at vref + 100mv uv vout first pwm pulse -100mv ss settling at vref + 100mv figure 8. soft-start with vout = uv ov = 113% vout target voltage first pwm pulse figure 9. soft-start with vout below ov but above final target voltage figure 10. power-good threshold window -13% -9% v ref +9% +13% vmon1, 2 uv uv pre-ov (no latch) < +20% channel 2 uv/ov end of ss1 and pgood channel 1 uv/ov end of ss2 or +20% good good isl8120irzec
24 fn6763.1 april 21, 2009 both channels share the same pgood output. either of the channels indicating out-of-regulation will pull-down the pgood pin. the power-good comparators monitor the voltage on the vmon pins. the trip points are shown in figure 10. pgood will not be asserted until after the completion of the soft-start cycle of both channels. if channels 1 or 2 are not used, the power-good can stay in operation by connecting 2 channels? vmon pins together. the pgood pulls low upon both en/ff?s disabling it if one of the vmon pins? voltage is out of the threshold window. pgood will not pull low until the fault presents for three consecutive clock cycles. in du al/ddr applicat ion, if the turn-off channel pre-charge s its vmon within the pgood threshold window, it could indicate power-good, however, the pgood signal can pull low with an external pnp or pmos transistor via the en/ff of the corresponding off channel. undervoltage and overvoltage protection the undervoltage (uv) and overvoltage (ov) protection circuitry monitor the voltage on the vmon pins. the uv functionality is not enabled until the end of soft-start. an ov condition (>120%) during soft-start would latch ic off. in an uv event, if the output drops below -13% (-9% is the hysteresis level) due to some reasons other than ov, oc, ot, and pll faults (en/ff is not pulled low) of the target level at the output voltage falling edge, the lower mosfets will turn off to avoid any negative voltage ringing. an ov event (v out > 120%) causes the high-side mosfet to latch off permanently, while the low-side mosfet turns on and then turns off after the output voltage drops below 87%. at the same time, the en/ff and pgood are also latched low. the latch condition can be reset only by recycling vcc. in dual/ddr mode, each channel is responsible for its own ov event with the corresponding vmon as the monitor. in multiphase mode, both channels respond simultaneously when either triggers an ov event . to protect the overall power trains in case of only one channel of a multiphase syst em detecting ov, the low-side mosfet always turns on at the conditions of en/ff = low and the output voltage above 113% (all vmon pins and en pins are tied together) and turns off after the output drops below 87%. thus, in a high phase count application (multiphase mode), all cascaded ics can latch off simultaneously via en pins, and each ic shares the same sink current to reduce the stress and eliminate the bouncing among phases. pre-por overvoltage pr otection (pre-por-ovp) when both the vcc and pvcc are below pors (not include en por), the ugate is low and lgate is floating (high impedance). en/ff has no control on lgate when below pors. when above pors, the lgate would not be floating but toggling with its pwm pulses. an external 10 resistor, connected in between phase and lgate nodes, enables the pre-por-ovp circuit. the output of the converter that is equal to phase node voltage via output inductors is then effectively clamped to the low-side mosfet?s gate threshold voltage, which provides some protection to the microprocessor if the upper mosfet(s) is shorted during start-up, shutdown, or normal operations. for complete protection, the low-side mosfet should have a gate threshold that is much smaller than the maximum voltage rating of the load. the pre-por-ovp works against pre-biased start-up when pre-charged output voltage is higher than the threshold of the low-side mosfet, however, it can be disabled by placing a 2k resistor from lgate to ground. over-temperature protection (otp) when the junction temperature of the ic is greater than +150c (typically), both en/ff pi ns pull low to inform other cascaded channels via their en/ff pins. all connected en/ffs stay low and release after the ic?s junction temperature drops below +125c (typically), with a +25c hysteresis (typical). figure 11. force lgate high logic en/ff1 force vmon1 lgate1 high 113% 87% en/ff2 force vmon2 lgate2 high 113% 87% vmon1>120% vmon2>120% multiphase mode = high or or or and and and figure 12. uv and ov timing diagram uv ov latch 3 cycles vout pgood ugate and en/ff latch low 3 cycles 120% isl8120irzec
25 fn6763.1 april 21, 2009 current loop when the isl8120irzec operates in 2-phase mode, the current control loop keeps the channel?s current in balance. after 175ns blanking period with respect to the falling edge of the pwm pulse of each channel, the voltage developed across the dcr of the inductor, r ds(on) of the low-side mosfets, or a precision resistor, is filtered and sampled for 175ns. the current (i cs1 /i cs2 ) is scaled by the r isen resistor and provides feedback proportional to the average output current of each channel. for dcr sensing, the ics can be derived from equation 2 : where il is the inductor dc current, and dcr is its dc resistance. for low-side mosfet r ds(on) sensing, the ics can be derived from equation 3 : in multiphase mode (vsen2- pulled high), the scaled output currents from both active channels are combined to create an average current reference (i avg ) which represents average current of both channe l outputs as calculated in equation 4. isen1b isen1a 700mv vcc dcr1 dcr2 amp amp vsen2- + + ishare i cs2 i cs1 current share block i avg current correction block current correction block vsen2+ 2 + - channel 1 pwm control block channel 2 pwm control block channel 1 soft-start and channel 2 soft-start and fault logic avg_oc comp oc2 comp figure 13. simplified current sampling and overcurrent protection i trip = 105a i csh_err - - - + i avg_cs v ishare iset 1.2v r iset i csh_err = (v isare - v iset )/g cs i avg_cs = i avg or i cs1 i avg = (i cs1 + i cs2 )/2 7 cycles delay i trip =105a 7 cycles delay e/a isen2b isen2a r c r isen2 vout phase2 iout2 dcr2 l2 fault logic channel 1 channel 2 r c r isen1 vout phase1 iout1 dcr1 l1 vout phase1 iout1 l1 isen1a dcr sensing r isen1 isen1b dcr1 r ds(on) sensing oc1 comp i avg_cs +15a i avg_cs +15a ics il dcr ? risen ------------------------ - = (eq. 2) ics il r ds on () ? risen --------------------------------- - = (eq. 3) iavg ics1 ics2 + 2 ----------------------------------- = (eq. 4) isl8120irzec
26 fn6763.1 april 21, 2009 the signal i avg is then subtracted from the individual channel?s scaled current (i cs1 or i cs2 ) to produce a current correction signal for each c hannel. the current correction signal keeps each channel?s output current contribution balanced relative to the other active channel. for multiphase operation, the share bus (v ishare ) represents the average current of all active channels and compares with each ic?s average current (i avg_cs equals to i avg or i cs1 depending upon the configuration, represented by v iset ) to generate current share error signal (i cs_err ) for each individual channel. each current correction signal is then subtracted from the error am plifier output and fed to the individual channel pwm circuits. when both channels operate independently, the average function is disabled and generates zero average current (i avg = 0), and current correction block of channel 2 is also disabled. the i avg_cs is the channel 1 current i cs1 . the channel 1 makes any necessary current correction by comparing its channel current (represented by v iset ) with the share bus (v ishare ). when the share bus does not connect to other ics, the iset and ishare pins can be shorted together and grounded via a single resistor to ensure zero share error. note that the common mode input voltage range of the current sense amplifiers is vcc - 1.8v. therefore, the r ds(on) sensing should be used for applications with output voltage greater than vcc - 1.8v. for example, application of 3.3v output is suggested to use r ds(on) sensing. in addition, the r-c network components (for dcr sensing) are selected such that the rc time constant matches the inductor l/dcr time constant. otherwise, it could cause undershoot/overshoot during load transient and start-up. c is typically set to 0.1f or higher, while r is calculated with equation 5. figure 13 shows a simple and flexible configuration for both r ds(on) and dcr sensing. current share control in multiphase single output the i avg_cs is the average current of both channels (i avg, 2-phase mode) or only channel 1 (i cs1, any other modes). ishare and iset pins source a copy of i avg_cs with 15a offset, for example, the full-scale will be 120a. if one single external resistor is used as r ishare connecting the ishare bus to ground for all the ics in parallel, r ishare should be set equal to r iset /n ctrl (where n cntl is the number of the isl8120irzec controllers in parallel or multiphase operations), and the share bus voltage (v ishare ) set by the r ishare represents the average current of all active channels. another way to set r ishare is to put one resistor in each ic?s ishare pin and use the same value with r iset (r ishare = r iset ), in which case the total equivalent resistance value is also r iset /n ctrl . the voltage (v iset ) set by r iset represents the average current of the corresponding device and compared with the share bus (v ishare ). the current share error signal (i csh_err ) is then fed into the current correction block to adjust each channel?s pwm pulse accordingly. the current share function prov ides at least 10% overall accuracy between ics, 5% within the ic when using a 1% resistor to sense a 10mv signal. the current share bus works for up to 12-phase. for multiphase implementation, one single error amplifier should be used for the voltage loop. therefor e, all other r l cdcr ? ----------------------- - = (eq. 5) figure 14. simplified current share and internal balance implementation ishare current mirror block i avg_cs iset v error1 + - i cs1 - error amp 1 v error2 + - i cs2 - error amp 2 current mirror block i avg_cs 700mv vcc vsen2- - - + + i csh_err i csh_err share bus r iset r ishare r ishare = r iset /n ctrl i droop + 15 a = i avg_cs + 15 a = iset = ishare i avg_cs = i avg or i cs1 i avg = (i cs1 + i cs2 ) / 2 isl8120irzec
27 fn6763.1 april 21, 2009 channels? error amplifiers should be disabled with their corresponding vsen- pulled to vc c, as shown in figure 15. current share control loop in multi-module with independent voltage loop the power module controlled by isl8120irzec with its own voltage loop can be paralleled to supply one common output load with its integrated maste r-slave current sharing control, as shown in ? typical application v iii (multiple power modules in parallel with current sharing control) ? on page 12. a resistor r csr needs to be inserted between vsen1- pin and the lower resi stor of the voltage sense resistor divider for each module. with this resistor, the correction current sourcing fr om vsen1- pin will create a voltage offset to maintain even current sharing among modules. the recommended value for the vsen1- resistor r csr is 100 and it should not be large in order to keep the unity gain amplifier input pin impedance compatibility. the maximum source current from vsen1- pin is 350a, which is combined with r csr to determine the current sharing regulation range. the generated correction voltage on r csr is suggested to be within 5% of vref (0.6v) to avoid fault trigging of uv/ov and pg ood during dynamic events. to attain good current balance in system start up preventing single module from overcurrent, the paralleled modules are recommended to be synchronized and the enable pins (en/ff) should be tied together to initial start-up at the same instant. overcurrent protection the ocp function is enabled at start-up. when both channels operate independently, the average function is disabled and generates zero average current (i avg = 0). the channel 2 current (i cs2 ) is compared with i trip (105a) and has its own independent ov ercurrent protection; while the 7 clock cycles delay is bypassed. the channel 1?s current (i cs1 ) plus 15a offset forms a voltage (v ishare ) with an external resistor r ishare and compares with a precision 1.2v threshold (1%, 50mv hysteresis); while the 105a ocp comparator with 7-cycl e delay is also activated. in multiphase operation, the v ishare represents the average current of all active channels and compares with a precision 1.2v threshold (1%, 50mv hysteresis) to determine the overcurrent condition, while each channel has additional overcurrent trip point at 105a with 7-cycle delay. this scheme helps protect against loss of channel(s) in multi-phase mode so that no single channel could carry more than 105a in such event. see figure 13. note that it is not necessary for the r ishare to be scaled to trip at the same level as the 105a ocp comparator if the application allows. for instance, when channel 1 operates independently, the oc trip set by 1.2v comparator can be lower than 105a trip point as shown in equation 6. where n is the number of phases; ncntl is the number of the isl8120irzec controllers in parallel or multiphase operations; i trip = 105a; ioc is the load overcurrent trip point; t min_off is the minimum ugate turn off time that is 350ns; r ishare in equation 6 represents the total equivalent resistance in ishare pin bus of all ics in multiphase or module parallel operation. the overcurrent trip current source is trimmed to 105a 10% for both channels, while the overcurrent threshold (represented by v ishare ) for multiphase operation (or channel 1 depending upon configur ation) is a precision 1.2v 1% with 50mv hysteresis. for the r isen chosen for ocp setting, the final value is usually higher than the number calculated from equation 6. figure 15. simplified 6-phase single output implementation ishare iset share bus r iset1 r ishare1 isl8120irzec 1 vsen1/2- com1/2 ishare iset r iset3 r ishare3 isl8120irzec 3 vsen1/2- com1/2 ishare iset r iset2 r ishare2 isl8120irzec 2 vsen2- com1/2 vcc vsen1+ vsen1- r ishare_ = r iset_ r isen1 i oc n --------- - v out l --------------- - 1d ? 2f sw ---------------- t min_off ? ?? ?? ? + ?? ?? ?? dcr ? i trip ---------------------------------------------------------------------------------------------------------------------- = r ishare 1v i trip -------------- - = r iset r ishare n cntl ? = (eq. 6) isl8120irzec
28 fn6763.1 april 21, 2009 the reason of which is practical especially for low dcr applications the pcb and inductor pad soldering resistance would have large effects in total impedance affecting the dcr voltage to be sensed. when ocp is triggered, the controller pulls en/ff low immediately to turn off ugate and lgate. however, if the output overshoot is greater t han 113% at en/ff = low, lgate turns on until the output voltage drops below 87%. a delay time, equal to 3 soft-start intervals, is entered to allow the disturbance to clear. after the delay time, the controller then initiates a soft-start interval. if the output voltage comes up and returns to the regulation, pgood transitions high. if the oc trip is exceeded during the soft-start interval, the controller pulls en/vff low again. the pgood signal will remain low and the soft-start interval will be allowed to expire. another soft-start interval will be initiated after the delay interval. if an overcurrent trip occurs again, this same cycle repeats until the fault is removed. there is a100ns delay to prev ent any fault triggering during start-up or load transient. for a hard short of the output, the overcurrent protection reduc es the regulator rms output current much less than 60% of the full load current by putting the controller into hiccup mode. internal series linear and power dissipation the vin pin is connected to pvcc with an internal series linear regulator (1w typical), which is internally compensated. the pvcc and vin pins should have the recommended bypasses connected to gnd for proper operation. the internal series linear regulator?s input (vin) can range between 3v to 22v. the internal linear regulator is to provide power for both the internal mosfet drivers through the pvcc pin and the analog circuitry through the vcc pin. the vcc pin should be connected to the pvcc pin with an rc filter to prevent hi gh frequency driver switching noise from entering the analog circuitry. when vin drops below 5.0v, the pass element will saturate; pvcc will track vin, minus the dropout of t he linear regulator. when used with an external 5v supply, vin pin is recommended to be tied directly to pvcc. the ldo is capable to supply 250ma with regulated 5.4v output. in 3.3v input applications, when the vin pin voltage is 3v, the ldo still can supply 150ma while maintaining ldo output voltage higher than vcc falling threshold to keep ic operating. figure 17 shows the ldo voltage drop under different load current. however, its thermal capability should not be exceeded. the power dissipation inside the ic could be estimated with equation 7. figure 16. internal regulator implementation 5v z1 3v to 26.4v 2.65v to 5.6v pvcc vin vcc z2 2 1f 10f p ic vin pvcc ? () i vin ? p dr + = (eq. 7) i vin q g1 n q1 ? v gs1 ----------------------------- - q g2 n q2 ? v gs2 ----------------------------- - + ?? ?? ?? pvcc f ? sw i q_vin + ? = figure 17. pvcc vs vin voltage 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 vin pin voltage (v) pvcc (v) iq is around 15ma pvcc @ 250ma + iq pvcc @ 100ma + iq pvcc @ 140ma + iq isl8120irzec
29 fn6763.1 april 21, 2009 where the gate charge (q g1 and q g2 ) is defined at a particular gate to source voltage (v gs1 and v gs2 ) in the corresponding mosfet datasheet; i q_vin is the driver?s total quiescent current with no load at drive outputs; n q1 and n q2 are number of upper and lower mosfets, respectively. to keep the ic within its operating temperature range, an external power resistor could be used in series with vin pin to bring the heat out of the ic, or and external ldo could be used when necessary. oscillator the oscillator is a sawtooth waveform, providing for leading edge modulation with 350ns minimum dead time. the oscillator (sawtooth) wavefo rm has a dc offset of 1.0v. each channel?s peak-to-peak of the ramp amplitude is set to proportional the voltage applied to its corresponding en/ff pin. see ? voltage feed-forward ? on page 22 . frequency synchronization and phase lock loop the fsync pin has two primary capabilities: fixed frequency operation and synchronized fre quency operation. by tying a resistor (r fsync ) to gnd from fsync pin, the switching frequency can be set at any frequency between 150khz and 1.5mhz. frequency setting curve shown in figure 20 are provided to assist in selecting the correct value for r fsync . by connecting the fsync pin to an external square pulse waveform (such as the clock signal, typically 50% duty cycle from another isl8120irzec), the isl8120irzec will synchronize its switching frequency to the fundamental frequency of the input waveform. the maximum voltage to fsync pin is vcc + 0.3v. the frequency synchronization feature will synchronize the leading edge of clkout signal with the falling edge of channel 1?s pwm clock signal. the clkout is not avail able until the pll locks. the locking time is typically 130s for f sw = 500khz. en/vff1 is released for a so ft-start cycle until the fsync stabilized and the pll is in locking. the pll circuits control only en/ff1, and control channel 2?s soft-start instead of en/ff2. therefore, it is recommended to connect all en/ff pins together in multiphase configuration. the loss of a synchronization signal for 13 clock cycles, the ic is disabled until the pll returns locking, at which point a soft-start cycle is initiated and normal operation resumes. holding fsync low will disable the ic. figure 18. typical upper-gate drive turn-on path figure 19. typical lower-gate drive turn-on path p dr p dr_up p dr_low + = (eq. 8) p dr_up r hi1 r hi1 r ext1 + -------------------------------------- r lo1 r lo1 r ext1 + ---------------------------------------- + ?? ?? ?? p qg_q1 2 --------------------- ? = p dr_low r hi2 r hi2 r ext2 + -------------------------------------- r lo2 r lo2 r ext2 + ---------------------------------------- + ?? ?? ?? p qg_q2 2 --------------------- ? = r ext2 r g1 r gi1 n q1 ------------- + = r ext2 r g2 r gi2 n q2 ------------- + = p qg_q1 q g1 pvcc 2 ? v gs1 -------------------------------------- - f sw ? n q1 ? = p qg_q2 q g2 pvcc 2 ? v gs2 -------------------------------------- - f sw ? n q2 ? = q1 d s g r gi1 r g1 boot r hi1 c ds c gs c gd r lo1 phase pvcc ugate pvcc q2 d s g r gi2 r g2 r hi2 c ds c gs c gd r lo2 gnd lgate figure 20. r fs vs switching frequency 0 200 400 600 800 1,000 1,200 1,400 1,600 20 40 60 80 100 120 140 160 180 200 220 240 260 r_fs (k ) switching frequency (khz) isl8120irzec
30 fn6763.1 april 21, 2009 differential amplifier for remote sense the differential remote sense buffer has a precision unity gain resistor matching network, which has a ultra low offset of 1mv. this true remote sensing scheme helps compensate the droop due to load on the positive and negative rails and maintain the high system accuracy of 0.6%. the output of the remote sense buffer is connected directly to the internal ov/uv comparat or. as a result, a resistor divider should be placed on the input of the buffer for proper regulation, as shown in figure 24. the vmon pin should be connected to the fb pin by a standard feedback network. since the input impedance of vsen+ pin in respect to vsen- pin is about 500k , it is highly recommended to include this impedance into calculation and use 100 or less for the lower leg (r os ) of the feedback resistor divider to optimize system accuracy. note that any rc filter at the inputs of differential amplifier will contribute as a pole to the overall loop compensation. as some applications will not need the differential remote sense, the output of the remote sense buffer can be disabled and be placed in high imp edance by pulling vsen- within 700mv of vcc. in such an event, the vmon pin can be used as an additional monitor of the output voltage with a resistor divider to protect the system against single point of failure, which occurs in the system using the same resistor divider for the uv/ov comparator and the output regulation. the resistor divider ratio should be the same as the one for the output regulation so that the correct voltage information is provided to the ov/uv comparator. figure 22 shows the differential sense amplifier can directly used as a monitor without pulling vsen- high. ddr and dual mode operation if the clkout/refin is less than 800mv, an external soft-start ramp (0.6v) can be in parallel with the channel 2?s internal soft-start ramp for ddr/tracking applications (ddr mode). the output voltage (typical vtt output) of channel 2 tracks with the input voltage (typical vddq*(1 + k) from channel 1) at the clkout/refin pin. as for the external input signal and internal reference signal (ramp and 0.6v), the one with the lowest voltage will be the one to be used as the reference comparing with fb signal. since the uv/ov comparator uses the same internal reference 0.6v, to guarantee uv/ov and pre-char ged start-up functions of channel 2, the target voltage derived from channel 1 (vddq) should be scaled close to 0.6v, and it is suggested to be slightly above (+2%) 0.6v with an external resistor divider, which will have the channel 2 use the internal 0.6v reference after soft-start. any capacitive load at refin pin should not slow down the ramping of this input 150mv lower than the channel 2 internal ramp. otherwise, the uv protection could be fault triggered prior to the end of the soft-start. the start-up of channel 2 can be delayed to avoid such situation happening, if high capacitive load presents at refin pin for noise decoupling. during shutdown, channel 2 will follow channel 1 until both channels drops below 87%, at which both channels enter uv protection zone. depending on the figure 21. equivalent differential amplifer 20k 20k 20k 20k r dif = 500k vsen- vsen+ gnd vsen+ vsen- fb vmon r fb r os ov/uv error amp comp 700mv vcc figure 22. dual output voltage sense fo r single point of failure protection v ref vout gain=1 pgood pgood z comp r os comp r fb isl8120irzec
31 fn6763.1 april 21, 2009 loading, channel 1 might drop faster than channel 2. to solve this race condition, channel 2 can either power up from channel 1 or bridge the channel 1 with a high current schottky diode. if the system requires to shutdown both channels when either has a fault, tying en/ff1 and en/ff2 will do the job. in ddr mode, channel 1 delays 60 over channel 2. in dual mode, depending upon the resistor divider level of refin from vcc, the isl8120i rzec operates as a dual pwm controller for two independent regulators with a phase shift as shown in table 2. the phase shift is latched as vcc raises above por and cannot be changed on-the-fly. internal reference and system accuracy the internal reference is set to 0.6v. including bandgap variation and offset of differential and error amplifiers, it has an accuracy of 0.9% over industrial temperature range. while the remote sense is not used, its offset (v os_da ) should be included in the tolerance calculation. equations 9 and 10 show the wors t case of system accuracy calculation. v os_da should set to zero when the differential amplifier is in the loop, the differential amplifier?s input impedance (r dif ) is typically 500k with a tolerance of 20% (r dif %) and can be neglected when r os is less than 100 . to set a precision setpoint, r os can be scaled by two paralleled resistors . table 2. mode decoding refin range phase for channel 2 wrt channel 1 required refin ddr <29% of vcc -60 0.6v dual 29% to 45% of vcc 0 37% vcc dual 45% to 62% of vcc 90 53% vcc dual 62% to vcc 180 vcc 700mv figure 23. simplified ddr implementaion phase-shifted clock vcc clkout/refin vsen2- vddq r k vddq 0.6v ------------------ 1 ? = k*r internal ss isl8120irzec state machine e/a2 0.6v fb2 vsen- vsen+ comp fb vmon r fb r os z fb z comp ov/uv error amp comp c sen 700mv vcc figure 24. simplified remo te sensing implementation v ref 10 10 vout (local) gnd (local) vsense+ (remote) gain=1 vsense- (remote) pgood pgood isl8120irzec
32 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6763.1 april 21, 2009 figure 25 shows the tolerance of various output voltage regulation for 1%, 0.5%, and 0.1% feedback resistor dividers. note that the farthe r the output voltage setpoint away from the internal reference voltage, the larger the tolerance; the lower the resistor tolerance (r%), the tighter the regulation. %min vref 1 ref% ? () ? v os_da ? () 1 r fb 1r% ? () ? r osmax ---------------------------------------- + ?? ?? ?? ? = (eq. 9) r osmax 1 1 r os 1r% + () ? ----------------------------------------- 1 r dif 1r dif % + () ? ---------------------------------------------------- + ---------------------------------------------------------------------------------------------------- - = %max vref 1 ref% ? () ? v os_da ? () 1 r fb 1r% ? () ? r osmin ---------------------------------------- + ?? ?? ?? ? = (eq. 10) r osmin 1 1 r os 1r ? % () ? -------------------------------------- - 1 r dif 1r dif ? % () ? ------------------------------------------------- + ----------------------------------------------------------------------------------------------- = figure 25. output regulation with different resistor tolerance for ref% = 0.6% output regulation (%) output voltage (v) -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 1% 0.5% 0.5% 0.1% 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 r% = 1% 0.1% isl8120irzec
33 fn6763.1 april 21, 2009 isl8120irzec package outline drawing l32.5x5b 32 lead quad flat no-lead plastic package rev 2, 11/07 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view 5.00 a 5.00 b index area pin 1 6 (4x) 0.15 32x 0.40 0.10 4 a 32x 0.23 m 0.10 c b 16 9 4x 0.50 28x 3.5 6 pin #1 index area 3 .30 0 . 15 0 . 90 0.1 base plane see detail "x" seating plane 0.10 c c 0.08 c 0 . 2 ref c 0 . 05 max. 0 . 00 min. 5 ( 3. 30 ) ( 4. 80 typ ) ( 28x 0 . 5 ) (32x 0 . 23 ) ( 32x 0 . 60) + 0.07 - 0.05 17 25 24 8 1 32

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